The conversion of digital signals to different sample rates suitable for various digital components and processes is well known. Digital signal processing systems use different sampling rates in various system components depending on a desired signal quality, noise density, required bandwidth, latency requirements, processing economy, available silicon area and other considerations. In conventional systems, cascaded integrator-comb (CIC), finite impulse response (FIR) and infinite impulse response (IIR) filters have been used to perform sample rate conversion, typically in multiple stages to save power, e.g., each successive stage will use a lower or higher sampling rate depending on whether the operation is decimation or interpolation. There is a continued need to lower the power consumption of sample rate conversion structures, lower delays within sample rate conversion structures, and lower the required silicon area for implementing sample rate conversion structures.